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A Special Unit to Speed Up a DSP Processor false
By:Uday Kumar Reddy Chenna Subbanagari
Published on 2016 by

Abstract: Digital Signal Processing (DSP) processors are used in personal computers, smart phones, multimedia devices, etc. Traditional DSP processors with custom logic must meet the demand for increased processing speed. The main aim of the project is to design a 32-bit integer arithmetic processor and to implement it. This design has three major processing features. First, the speed must be optimized by using a hazard free control unit. Second, it must have a two stage pipeline. Third, a single cycle multiply accumulator is utilized. The main advantage of the two stage pipeline is that it can manipulate the instructions, and it can produce correct cycle timing even though there may be hazards. A reduced instruction set is used in this design. A filtering operation is included in order to differentiate the DSP processor from a traditional processor. The processor is designed using Harvard architecture in which both data memory and program memory are accessed simultaneously. This design increases the processing speed by 30%.

This Book was ranked at 5 by Google Books for keyword DSPs.

Book ID of A Special Unit to Speed Up a DSP Processor's Books is 6VRPAQAACAAJ, Book which was written byUday Kumar Reddy Chenna Subbanagarihave ETAG "xVzTiKnJOEY"

Book which was published by since 2016 have ISBNs, ISBN 13 Code is 9781339715391 and ISBN 10 Code is 1339715392

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