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There are many applications in the field of digital signal processing (DSP) and controls that require the user to know how various numerical errors (uncertainty) affect the result. Interval Arithmetic (IA) eliminates this uncertainty by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. This thesis proposes a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division is not implemented on digital signal processors traditionally unless computed with a shift operation. In this design, division by shifting is implemented. One of the prime design goals is to maximize the throughput of the ALU for an optimum value of area. Pipelining is implemented to achieve this design goal. Power dissipation analysis of different ALU architectures is done. Since it required to obtain maximum throughput for the least power dissipation, throughput per unit power dissipation is used as the most critical performance metric. This thesis studies several architectures for the ALU and concludes with the one with the highest performance amongst the ones which are studied.

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